Title :
A high speed transmission/reception circuit for HDTV encoder based on parallel FIFO structure
Author :
Yingqi, Chen ; Yang Xiao Kang ; Songyu, Yu
Author_Institution :
Inst. of Image Commun. & Inf. Process., Shanghai Jiaotong Univ., China
Abstract :
A data transmission/reception circuit based on parallel FIFO storage structure is introduced. It is used as a video data testing source for an HDTV encoder or used for encoded data test and analysis. It is designed for being inserted in a PC´s AT bus. Under the control of a PC, it can transmit or receive data at very high speed. Its function, structure, characteristics and limits are explained, especially some design methods and design thoughts for increasing speed and storage scale as well as decreasing cost. The test results are also given.
Keywords :
add-on boards; high definition television; parallel architectures; telecommunication equipment testing; video coding; video equipment; AT bus; HDTV encode; data transmission/reception circuit; design; high speed transmission/reception circuit; parallel FIFO structure; speed; storage scale; video data testing source; Circuit testing; Clocks; Data communication; Decoding; Design methodology; Frequency; HDTV; High definition video; Image storage; Information processing;
Conference_Titel :
Communications, 1999. APCC/OECC '99. Fifth Asia-Pacific Conference on ... and Fourth Optoelectronics and Communications Conference
Conference_Location :
Beijing, China
Print_ISBN :
7-5635-0402-8
DOI :
10.1109/APCC.1999.820437
