A pipelined hardware architecture of deblocking filter in H.264/AVC

To improve the performance of in-loop deblocking filter in H.264/AVC, this paper proposes a pipelined hardware architecture. A novel transposer design is presented and its hardware cost is reduced by 15% with forwarding logic to shift pixels. Through adopting a filtering order with vertical and horizontal edges processed alternately, on-chip memory is greatly saved and only two 32times32 bits SRAMs are employed as a buffer. The time to prepare and transfer the intermediate data is also reduced, and only 222 clock cycles are required to filter one macroblock. By processing strong and normal mode filtering simultaneously in a 5-stage pipeline, the proposed architecture can work at a maximum clock frequency of 200 MHz under 0.18 mum technology, and meet the real-time filtering requirement of high-definition (1920times1088) video at a frame rate up to 116 frames per second. Moreover, for applications with low power requirement, it only needs a working frequency of 55 MHz to realize real-time decoding of 1920times1088@30fps video.