Unified bit pattern for leading-zero anticipatory logic for high-speed floating-point addition

This paper describes a novel design of leading-zero anticipatory (LZA) logic with unified bit pattern for high-speed floating-point addition (FADD). Leading-zero anticipatory logic is a technique to calculate the number of leading zeros of result in parallel with the addition. However, the anticipation might be in error by one bit. Previous schemes to correct this error result in delay or hardware complexity increase. By the unified bit pattern applied, the amount of leading zeros is determined exactly without correction necessity concurrently with addition for the significand.