Title :
On chip network: topology design and evaluation using NS2
Author :
Ngo, Vu-Duc ; Choi, Hae-Wook
Author_Institution :
Syst. VLSI Lab., Inf. & Commun. Univ., Taejon
Abstract :
The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the ultra deep submicron technologies that arise from nonscalable global wire delay, failure to archive global synchronization, errors due to signal integrity, nonscalable bus based functional interconnection, etc. In this paper, we introduce interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS2
Keywords :
multiprocessor interconnection networks; network topology; packet switching; queueing theory; routing protocols; synchronisation; system-on-chip; NS2; buffer size; bus-based functional interconnection; chip design; communication protocol; computer network design; global synchronization; global wire delay; heterogeneous semiconductor intellectual property block; interconnected network topology; network topology design; on chip network; packet switched network; routing algorithm; routing strategy; signal integrity; switched network topology; ultra deep submicron technology; Algorithm design and analysis; Chip scale packaging; Communication switching; Intellectual property; Network topology; Network-on-a-chip; Packet switching; Performance analysis; Routing protocols; Wire;
Conference_Titel :
Advanced Communication Technology, 2005, ICACT 2005. The 7th International Conference on
Conference_Location :
Phoenix Park
DOI :
10.1109/ICACT.2005.246202
