Title :
A cost framework for evaluating integrated restructuring optimizations
Author :
Chandramouli, Bharat ; Carter, John B. ; Hsieh, Wilson C. ; McKee, Sally A.
Author_Institution :
Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
Abstract :
Loop transformations and array restructuring optimizations usually improve performance by increasing the memory locality of applications, but not always. For instance, loop and array restructuring can either complement or compete with one another. Previous research has proposed integrating loop and array restructuring, but there existed no analytic framework for determining how best to combine the optimizations for a given program. Since the choice of which optimizations to apply, alone or in combination, is highly application and input-dependent, a cost framework is needed if integrated restructuring is to be automated by an optimizing compiler. To this end, we develop a cost model that considers standard loop optimizations along with two potential forms of array restructuring: conventional copying-based restructuring and remapping-based restructuring that exploits a smart memory controller. We simulate eight applications on a variety of input sizes and with a variety of hand-applied restructuring optimizations. We find that employing a fixed strategy does not always deliver the best performance. Finally; our cost model accurately predicts the best combination of restructuring optimizations among those we examine, and yields performance within a geometric mean of 5% of the best combination across all benchmarks and input sizes
Keywords :
data structures; optimising compilers; program control structures; software performance evaluation; array restructuring optimizations; copying-based restructuring; cost framework; loop optimizations; loop transformations; memory locality; optimizing compiler; performance; remapping-based restructuring; smart memory controller; Application software; Automatic control; Bandwidth; Cost function; Delay; Hardware; Optimizing compilers; Predictive models; Size control; Software performance;
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on
Conference_Location :
Barcelona
Print_ISBN :
0-7695-1363-8
DOI :
10.1109/PACT.2001.953294