ASIC design of a Gbit/s LDPC decoder for iterative MIMO systems

The design of double-iterative systems like turbo synchronization or iterative demapping and decoding will be one of the big challenges in the next years. The components of such systems need to fulfill stringent conditions on throughput and flexibility thus making a reuse of available standard components difficult. We present a high throughput ASIC design for LDPC decoding in iterative MIMO systems with a high flexibility on block sizes (3720 to 14880 bits, granularity 186 bits) and code rates (1/2 to 4/5). After P&R, the ASIC design has an area of 4.588 mm² and consumes 1271 mW at a clock frequency of 275 MHz. The LDPC decoder has a throughput of 3.5 Gbit/s (@5 iterations) while the resulting iterative MIMO system (4 feedback loops with 5 LDPC iterations each) runs at 275 Mbit/s.