Title :
CMOS VLSI implementation of gigabyte/second computer network links
Author :
Bendak, Michael B. ; Fellman, Ronald D. ; Chau, Paul M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
High speed computer network links require a variety of on-chip system components in order to achieve optimal performance. These components include systems that provide clock generation and synchronization as well as line driver and receiver circuits for signal conditioning. This paper presents designs for a link synchronizer, a low voltage differential signal (LVDS) I/O system, and a phase locked loop for providing a system clock. Portions of these systems have been implemented in 2 μm and 1.2 μm MOSIS chips
Keywords :
CMOS digital integrated circuits; VLSI; computer interfaces; computer networks; data communication equipment; digital phase locked loops; network interfaces; synchronisation; timing circuits; 1.2 micron; 2 micron; 200 MHz; CMOS VLSI implementation; GB/s interface; LV differential signal I/O system; MOSIS chips; PLL; clock generation; gigabyte/second computer network links; high speed computer network; line driver circuits; line receiver circuits; onchip system components; phase locked loop; signal conditioning; synchronization; system clock; Clocks; Computer networks; Driver circuits; Low voltage; Network-on-a-chip; Signal design; Signal generators; Synchronization; System-on-a-chip; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541698
