Title :
Minimization of adders in fast FIR digital filters and its application to filter design
Author :
Yagyu, Mitsuhiko ; Nishihara, Akinori ; Fujii, Nobuo
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan
Abstract :
This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley´s technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. An algorithm is given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using MILP. Utilization of common expressions in Hartley´s technique widen the CSD coefficient space. Thus the mixed integer linear programming (MILP) may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations
Keywords :
FIR filters; Hartley transforms; adders; circuit analysis computing; critical path analysis; digital filters; frequency response; integer programming; minimisation; network synthesis; FIR digital filters; Hartley´s technique; adders; canonic signed digit code; filter coefficients; filter design; frequency responses; minimal number of adders; mixed integer linear programming; shortest critical path; simulation; subtractors; wired logic; Adders; Costs; Design methodology; Digital filters; Electronic mail; Finite impulse response filter; Frequency response; Hardware; Logic; Mixed integer linear programming;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541704