Use of Triple Modular Redundancy (TMR) technology in FPGAs for the reduction of faults due to radiation in the readout of the ATLAS monitored drift tube (MDT) chambers

The Triple Modular Redundancy (TMR) technology allows protection of the functionality of FPGAs against single event upsets (SEUs). Each logic block is implemented three times with a 2-out-of-3 voter at the output. Thus, the correct logical value is available even if there is an upset bit in one location. We applied TMR to the configuration code of a Virtex-II-2000 FPGA, which serves as the on-chamber readout processor of the ATLAS monitored drift tubes (MDTs). We describe the code implementation, results of performance measurements and discuss several limitations of the method. Finally, we present a supplementary technology called “scrubbing”. It permanently checks the configuration memory while the FPGA is operating, and corrects upset configuration bits when necessary.