RocketTC: A high throughput traffic classification architecture

Real-time traffic classification is becoming increasingly critical for network management, traffic engineering, and network security. Current software-based solutions, however, have difficulties dealing with a great number of flows in today´s high-speed networks. This paper proposes RocketTC, a scalable FPGA-based architecture, to accelerate traffic classification while maintaining high accuracy. It combines two significant elements: (1) an efficient flow management scheme using on-chip BRAMs for storing the flow table, and (2) a parallel and pipelined classification engine array with partial dynamic reconfiguration (PDR) on FPGA. We have implemented and evaluated RocketTC on Xilinx Virtex-5 FPGA based platform. Our results show a sustained throughput of over 20 Gbps for minimum packet size of 40 bytes, and high accuracy above 97% for classifying nearly a hundred popular applications. Additionally, it is easy for RocketTC to update more application types.