Title :
A cell selection algorithm for area minimization
Author :
Kim, Tae Hoon ; Kim, Young Hwan
Author_Institution :
Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea
Abstract :
This paper presents a cell selection algorithm that minimizes the area of the cell-based design, while satisfying the given delay constraint. The proposed algorithm visits the given circuit in the forward direction and calculates the lower bound on the delay and area. Then, it visits the circuit in the reverse direction, and binds the logic gates with library cells using the Branch-and-Bound formulations of the lower bound. Experimental results show that the proposed algorithm minimizes the area of test circuits by 27.33% on the average
Keywords :
VLSI; circuit optimisation; integrated circuit design; minimisation; VLSI design; area minimization; branch-and-bound technique; cell selection algorithm; circuit delay; logic gate; technology mapping; Algorithm design and analysis; Capacitance; Circuit testing; Data preprocessing; Delay estimation; Libraries; Logic design; Logic gates; Minimization methods; Space exploration;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.820810
