Subthreshold Logic Using Body-Bias Technique for Digital VLSI Neural Applications

The Electronic neuron is able to mimic the behavior of actual biological neuron with real time adaptability. For VLSI implementation, each building block for the neuron circuit is designed for low power and small silicon area. It is possible to process large quantities of sensory inputs in real time with low power operation using sub threshold techniques. Sub threshold MOS currents are comparable to ionic currents in cell membranes, which range from a few Pico amperes to a few microamperes. But in most of the implementations using sub threshold MOS circuits, body effect i.e. dependence of subthresdold current on potential difference between body and source terminal (VSB) is either neglected or it has not been taken into account. In this paper we have explored body bias technique to take into account the body effect. Extensive circuit simulations were conducted for with 180nm technology parameters at 0.5V to validate the proposed idea. The proposed body bias technique has improved power-delay product parameter for sub threshold digital circuits and thus has great degree of freedom in the design of low voltage digital VLSI circuits for neural applications.