A new analysis technique for the sensitivity of chip performance

In this paper, we introduce a state-of-the-art statistical modeling technique which is developed in order to evaluate the sensitivity of chip performance with device parameters using SPICE simulation. ET-based SPICE modeling links the shift of E-tests (Electrical tests) to a set of SPICE model parameters without additional measurements of I-V curves. Therefore, it is very useful and quick in analyzing the sensitivity of circuit characteristics to E-tests. In the case of an asynchronous DRAM, PMOS Idsat primarily contributes to the variation of the chip performance tRAC. This methodology not only enables circuit designers to analyze the circuit sensitivity with E-test, but also provides key device characteristics for the statistical process control during the yield ramp-up