High-speed FPGA-implementation of multidimensional binary morphological operations

Morphological operations are commonly used tools for the extraction of regional features and shape information in pattern recognition and image understanding tasks. In the present paper, a general approach for low-cost hardware-realization of multidimensional binary morphological operations is proposed. The underlying definitions of Minkowski addition and Minkowski subtraction are reduced to linear n-D convolutions, which lead to several alternative implementations. The flexible architecture of modern FPGAs allows the construction of operations with fixed and variable sized structuring elements that handle regions of up to 1000 object elements (e.g. pixels) in parallel. This leads to low-cost hardware realizations of real-time computer vision tasks. Possible clock frequencies of more than 100 MHz provide morphological image processing for camera resolution of 320×240 pixel at frame rates of over 1000 Hz.