Hardware synthesis for stack type partitioned-bus architecture

Due to an efficient interconnect structure and internal parallelism, partitioned-bus architecture is viable for deep sub-micron chip design. In this paper, we propose a new partitioned-bus architecture and its supporting high-level synthesis methodology. The new architecture extends an existing linear architecture by stacking multiple layers for handling large datapath intensive applications. Experiments show that the approach generates compact datapath layout with flexibility of aspect ratio and reduces average bus driving length