Title :
Hardware cost estimation techniques for C-level description
Author :
Kim, Tae-Woo ; Shin, Hyunchul
Author_Institution :
Dept. of Electron. Eng., Hanyang Univ., Kyunggi, South Korea
Abstract :
Recent trends in the hardware/software codesign and architectural exploration bring us the need to develop sophisticated high-level estimation tools. This paper describes hardware cost estimation techniques for descriptions written in C language. This approach estimates the area and performance of the system described in standard ANSI C language to be implemented in hardware. Experimental results show that this approach has some errors but gives the designer useful information concerning the hardware for architectural exploration and hardware/software partitioning in high-level codesign
Keywords :
C language; hardware description languages; hardware-software codesign; C language; C-level description; architectural exploration; hardware cost estimation techniques; hardware/software codesign; hardware/software partitioning; high-level codesign; high-level estimation tools; ANSI standards; Computer errors; Costs; Data mining; Delay estimation; Hardware design languages; Libraries; State estimation; Throughput; Timing;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.820831
