A high performance 0.13 μm CMOS process for GHz microprocessor manufacture

Author

Lee, Seung Woo ; Jeon, Sang Jung ; Park, Jong Chun ; Ahn, Jong Hyon ; Kim, Young Wug ; Suh, Kwang Pyuk

Author_Institution

Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

1999

fDate

1999

Firstpage

136

Lastpage

139

Abstract

A highly manufacturable and high performance 0.13 μm CMOS process for a 1.5 V microprocessor is proposed. The device is integrated by dual-doped poly-Si transistors with STI, additionally doped gate poly, highly doped drain extension and Co-salicide structure. Co-salicide gate with sheet resistance below 5 ohm/sq. in the 0.1 μm -length gate line is obtained. By using indium and boron as channel implants, and employing n⁺poly gates for nMOS while low-energy boron instead of BF2 is used for pMOS gates, the Idsat values of 770 μA/μm and 31 μA/μm have been achieved with the electrical gate oxide thickness of 2.6 nm and 2.8 nm for nMOS and pMOS, respectively

Keywords

CMOS digital integrated circuits; boron; high-speed integrated circuits; indium; integrated circuit manufacture; integrated circuit technology; ion implantation; microprocessor chips; silicon; 0.13 micron; 1.5 V; 2.6 nm; 2.8 nm; GHz microprocessor manufacture; STI; Si:B; Si:In; channel implants; co-salicide structure; doped gate polysilicon; dual-doped poly-Si transistors; high performance CMOS process; highly doped drain extension; low-energy B implant; n⁺poly gates; nMOS gates; pMOS gates; Boron; CMOS process; CMOS technology; Doping; Implants; MOS devices; Manufacturing processes; Microprocessors; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820850

Filename

820850