DocumentCode :
3528923
Title :
High aspect ratio via etching for dual damascene process in a inductively coupled plasma (ICP) etcher
Author :
Han, Kuk ; Cho, Woo Sung ; Park, Jae Hyun ; Ha, Jae Hee ; Park, Jin Won
Author_Institution :
Res. Center, Hyundai Micro Electron. Co. Ltd., Cheongeju, South Korea
fYear :
1999
fDate :
1999
Firstpage :
155
Lastpage :
158
Abstract :
Deep-via etching for a dual-damascene process adopting a via-first scheme was studied in an ICP etching system. Via etching in a structure compatible with 0.18 μm design rules requires process specifications such as high aspect ratio IMD (inter-metal dielectric) etching consisting of intermediate nitride and oxide layers, highly selective etching to photoresist (PR) and to the sub-underlying layer. In order to investigate the compromise between the main etch parameters, a statistical experimental design was performed. Oxide (TEOS) etch rate and selectivity to PR were evaluated as main responses and dc bias voltage was also monitored. PR selectivity increased with CO and CH2F2 gas flow rate, but pressure and top power have little effect on it. TEOS etch rate went up in proportional to top power, but CO gas flow rate and pressure showed a reverse trend. Additionally, while TEOS etch rate was inversely proportional to dc bias voltage, PR selectivity was independent of it. The optimized process conditions were applied to real deep via structures. Since both unselective etching for the intermediate nitride layer and highly selective etching for the sub-underlying layer were desired, two step etching was indispensable. Consequently, a vertical via profile with an aspect ratio of 5.3 was achieved through the IMD layers
Keywords :
VLSI; design of experiments; dielectric thin films; integrated circuit interconnections; photoresists; sputter etching; 0.18 mum; 13.56 MHz; CH2F2 gas flow rate; CO; CO gas flow rate; CO/C4F8/CH2F2; ICP etcher; TEOS etch rate; aspect ratio; dc bias voltage; deep-via etching; difluoromethane; dual damascene process; high aspect ratio IMD etching; high aspect ratio via etching; highly selective etching; inductively coupled plasma; inter-metal dielectric; intermediate nitride layers; octafluorobutane; optimized process conditions; oxide layers; photoresist selectivity; statistical experimental design; top power; two step etching; vertical via profile; via-first scheme; Dielectrics; Etching; Fluid flow; Integrated circuit interconnections; Plasma applications; Plasma density; Plasma sources; Resists; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
Type :
conf
DOI :
10.1109/ICVC.1999.820857
Filename :
820857
Link To Document :
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