Application of full chip OPC to quarter micron logic device

Author

Him, Kyung-JinS ; Park, Ki-Yeop ; Lee, Won Gyu ; Lee, Dai-Hoon

Author_Institution

Process Dev. Dept. 1, Hyundai Electron. Ind. Co. Ltd., Kyungki, South Korea

fYear

1999

fDate

1999

Firstpage

171

Lastpage

173

Abstract

Model based full chip Optical Proximity Correction (OPC) was applied to logic devices with a minimum gate length of 0.24 μm. Two empirical models were used in order to correct for both the 1D optical proximity effect and the 2D optical proximity effect simultaneously. OPC features such as line bias and hammer head were effective in reducing critical dimension variation and line shortening. Increased process margin and reduction in interconnection resistance were obtained

Keywords

integrated logic circuits; photolithography; proximity effect (lithography); semiconductor process modelling; ultraviolet lithography; 0.24 mum; 1D optical proximity effect; 2D optical proximity effect; DUV process; critical dimension variation; empirical models; full chip optical proximity correction; hammer head; i-line process; interconnection resistance reduction; line bias; line shortening; minimum gate length; model based full chip OPC; process margin; quarter micron logic device; Apertures; Coherence; Electronic mail; Linearity; Logic devices; Optical devices; Optical distortion; Optical interconnections; Proximity effect; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820864

Filename

820864