DocumentCode :
3529407
Title :
Gate oxide thinning effects at the edge of shallow trench isolation in the dual gate oxide process
Author :
Lee, Seok-Woo ; Cho, Ihl Hyun ; Park, Sang Hyuk ; Choi, Hong Goo ; Kim, Nam Gawk ; Kim, Jong-Kwan ; Han, Sang Beom ; Kyungho Lee
Author_Institution :
Adv. Process Dev. 2 Team, Hyundai MicroElectron. Co. Ltd., Cheongju, South Korea
fYear :
1999
fDate :
1999
Firstpage :
249
Lastpage :
252
Abstract :
We have investigated the degradation of thick gate oxide in the conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide operating under the bias of 1.8 and 2.5 V, respectively, on a single chip, a novel dual gate oxide process flow, without gate oxide thinning at STI corner, is presented. Our new integration of dual gate oxide shows an improved gate oxide reliability compared to the conventional process
Keywords :
CMOS integrated circuits; MOSFET; isolation technology; semiconductor device breakdown; semiconductor device reliability; 1.8 V; 2.5 V; 3 nm; 6 nm; CMOS processing; breakdown voltage distribution; charge to breakdown; dual gate oxide process; gate oxide reliability; gate oxide thinning effects; shallow trench isolation; thick gate oxide degradation; CMOS logic circuits; Contamination; Degradation; Design for quality; Oxidation; Planarization; Plasma temperature; Resists; Voltage; Wet etching;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
Type :
conf
DOI :
10.1109/ICVC.1999.820895
Filename :
820895
Link To Document :
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