Compact digital memory blocks for the DSSC pixel readout ASIC

The European XFEL will have a burst rate of up to 5 MHz arranged in bunch trains each comprising up to 3000 pulses. The inter bunch train rate will be 10 Hz. The pixel readout of the DSSC (DEPFET Sensor with Signal Compression) foreseen for this machine will immediately digitize all analogue charges. The digital data is then stored locally within the pixels before it is read out. In order to accumulate a maximum number of events during the XFEL bunch trains, a compact digital memory solution is required. Relatively slow concepts can be implemented because access times of >; 200 ns are required. Readout of the pixel memories will be done in between of the XFEL bunch trains. We have therefore designed and tested two compact storage solutions based on static or dynamic storage in the IBM 130 nm technology, both of them using only three metalization layers within the pixels. The DSSC readout chip will comprise 4096 pixels, each pixel having a size of 229 mm × 204 μm. One third of the pixel has been allocated for the digital storage.