A fast synchronous pipelined DRAM (SP-DRAM) architecture with SRAM buffers

Author

Yoon, Chi-Weon ; Im, Yon-Kyun ; Han, Seon-Ho ; Hoi-Jun Yoo ; Jung, Tae-Sung

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

fYear

1999

fDate

1999

Firstpage

285

Lastpage

288

Abstract

We propose a Synchronous Pipelined DRAM (SP-DRAM) architecture which has a fast row-cycle. Pipeline circuitry is inserted in the row path and multiple SRAM buffers are integrated in the DRAM to reduce row latency. The data transfer rate of the SP-DRAM is measured to be faster by 40% than SDRAM and by 20% than VCM as a result of system level performance analysis. A partial activation scheme is adopted in the cell core to reduce unnecessary power consumption. The SP-DRAM can maintain compatibility with a conventional SDRAM interface with negligible performance degradation

Keywords

CMOS memory circuits; DRAM chips; SRAM chips; buffer storage; high-speed integrated circuits; parallel memories; pipeline processing; 0.35 mum; 64 Mbit; CMOS technology; SDRAM interface compatibility; SRAM buffers; address-multiplexing scheme; data transfer rate; fast row-cycle; fast synchronous pipelined DRAM architecture; partial activation scheme; power consumption reduction; row latency reduction; system level performance analysis; Bandwidth; Circuits; Degradation; Delay; Electronic mail; Energy consumption; Performance analysis; Pipelines; Random access memory; SDRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820907

Filename

820907