DocumentCode :
3529921
Title :
SIFU!-a didactic stuck-at fault simulator
Author :
Correia, Vinícius P. ; Lubaszewski, Marcelo ; Reis, André I.
Author_Institution :
Inst. de Inf., UFRGS, Porto Alegre, Brazil
fYear :
2003
fDate :
1-2 June 2003
Firstpage :
93
Lastpage :
94
Abstract :
This paper presents a didactic simulator for stuck-at (sa) faults on logic circuits. The tool has a set of features that helps to understand the concepts of single and multiple stuck-at faults, being these faults testable or not, and how to generate test vectors in order to test the detectable fault subset. An interface was developed to allow the edition of a circuit, the injection of faults and the fault simulation. The tool performs two simulations concurrently, one for the original circuit and another for the faulty circuit considering the injected faults. When the two simulations differ, for a given input vector, the tool shows the error (detection of the fault) graphically.
Keywords :
combinational circuits; fault simulation; logic testing; software tools; didactic simulator; fault detection; fault injection; fault simulation; fault subset; faulty circuit; logic circuit; multiple stuck-at faults; single stuck-at fault; test vector generation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Electrical fault detection; Fault detection; Logic circuits; Power supplies; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Systems Education, 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN :
0-7695-1973-3
Type :
conf
DOI :
10.1109/MSE.2003.1205270
Filename :
1205270
Link To Document :
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