Internet-based tool for system-on-chip integration

A tool has been created for use in a design course to automate integration of new components into a System-On-Chip(SOC). Students used this tool to implement a complete SOC Internet firewall, which was prototyped and tested using a field-programmable gate array (FPGA). Common components of the framework were completed as machine problem assignments throughout the first half of the semester. During the second half of the semester, students worked in small groups to design extensible modules, which included additional packet filters, a packet encryption engine, and replacement schedulers to enhance the functionality of the SoC firewall. The integration tool was used to manage project submissions and to synthesize designs for testing and project evaluation.