Internet-based tool for system-on-chip project testing and grading

Author

Zuver, Christopher K. ; Neely, Christopher E. ; Lockwood, John W.

Author_Institution

Dept. of Comput. Sci. & Eng., Washington Univ., Saint Louis, MO, USA

fYear

2003

fDate

1-2 June 2003

Firstpage

119

Lastpage

120

Abstract

A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FPGA hardware over the internet. A web interface allows students to upload their placed and routed designs to the server, which batches the jobs together and (1) sequentially programs an FPGA board, (2) inputs test vectors, (3) generates a report that details the results, and (4) grades the design as either "pass" or "fail." The single server allows an entire class to share the same FPGA board.

Keywords

Internet; circuit testing; design engineering; electronic design automation; field programmable gate arrays; logic CAD; network servers; student experiments; system-on-chip; FPGA board; FPGA hardware circuits; Internet; Internet-based tool; Web interfaces; electronic design automation; field programmable gate array; reprogrammable hardware; sequential programs; server; system-on-chip project; Automatic testing; Circuit testing; Field programmable gate arrays; Hardware; Internet; Job design; Sequential analysis; System testing; System-on-a-chip; Web server;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Systems Education, 2003. Proceedings. 2003 IEEE International Conference on

Print_ISBN

0-7695-1973-3

Type

conf

DOI

10.1109/MSE.2003.1205282

Filename

1205282