DocumentCode
3530107
Title
Developing a teaching environment for rapid design and verification of complex digital/computing systems
Author
Hung, Donald ; Vien, John ; Chan, Wendy ; Fu, Chi-Wei
Author_Institution
Dept. of Comput. Eng., San Jose State Univ., CA, USA
fYear
2003
fDate
1-2 June 2003
Firstpage
131
Lastpage
133
Abstract
This paper first discusses the need and difficulties for the education community to establish an environment to teach system-level design and verification, then describes the activities at San Jose State University (Computer Engineering Department) in developing such an environment through a low cost approach. A demo is provided along with the paper.
Keywords
computer science education; digital systems; hardware description languages; system-on-chip; teaching; San Jose state university; complex digital/computing systems design; complex digital/computing systems verification; system-level design education; system-level verification education; system-on-chip; Computer science education; Costs; Design engineering; Educational products; Hardware; Silicon; System-level design; System-on-a-chip; Systems engineering education; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Systems Education, 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN
0-7695-1973-3
Type
conf
DOI
10.1109/MSE.2003.1205287
Filename
1205287
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