Title :
Process variation study of Ground Plane SOI MOSFET
Author :
Saremi, Mehrin ; Ebrahimi, B. ; Kusha, Ali Afzali ; Saremi, Mehrin
Author_Institution :
Nanoelectron. Center of Excellence, Univ. of Tehran, Tehran, Iran
Abstract :
In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32 nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.
Keywords :
MOSFET; normal distribution; semiconductor thin films; silicon-on-insulator; transistor circuits; DIBL coefficient; GPS structure; SOI device structure; SOI-GPB; SOI-GPS; SOI-WGP; channel length; drain-induced barrier lowering; ground plane SOI MOSFET; ground-plane in box; ground-plane in substrate; normal distribution; process variation; short-channel effect; silicon-on-insulator; size 32 nm; subthreshold swing; thin-film thickness variation; threshold voltage; transistor; without ground plane; Global Positioning System; Isolation technology; Laboratories; MOSFET circuits; Nanoelectronics; Semiconductor thin films; Silicon on insulator technology; Substrates; Thin film transistors; Threshold voltage; Drain-Induced Barrier Lowering (DIBL); Ground Plane (GP); Process variations; Short-Channel Effects (SCEs); Silicon-On-Insulator (SOI) MOSFET;
Conference_Titel :
Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4244-7809-5
DOI :
10.1109/ASQED.2010.5548155
