High-speed and low-leakage MTCMOS memory registers

Various high speed sequential multi-threshold voltage CMOS (MTCMOS) circuit techniques are presented and evaluated in this paper. Dedicated low leakage data preserving memory elements are integrated into the MTCMOS flip-flops. The leakage power consumption of an MTCMOS memory register is reduced by up to 67.72% as compared to the previously published conventional sequential MTCMOS circuits in a UMC 80nm CMOS technology. The control scheme required to implement a low leakage sleep mode is significantly simplified with the memory register. Furthermore, the area of the memory register is reduced by up to 46.43% as compared to the conventional MTCMOS registers.