Block-based compressive sampling for digital pixel sensor array

In this paper, a block-based online compressive sampling scheme for digital pixel sensor (DPS) is proposed. The overall sensor array is divided into blocks whereby one randomly selected pixel within each block is sampled using a random access control circuit. The latter is performed using off-array horizontal and vertical control logic. The random access addresses are updated during readout phase using low complexity logic operations performed on the readout pixel values. A sparse matrix, consisting of all the sampled pixel values, is buildup to reconstruct the image by solving the l₁-norm minimization as the linear programming problem in the framework of Convex Optimization. The proposed system features reduced on-chip compression processing complexity and significant reduced memory requirement. System level simulation results show that a 25dB reconstructed image quality in terms of PSNR is achieved enabling a compression ratio of 4. In addition, a pixel-level memory requirement reduction of 75% is achieved when compared to a standard PWM DPS architecture.