Title :
Burst Mode Memories Improve Cache Design
Author :
Amitai, Zwie ; Wyland, David C.
Author_Institution :
Quality Semiconductor, Inc.
Abstract :
Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.
Keywords :
Cache memory; Clocks; Counting circuits; Delay effects; Engineering management; Planing; Quality management; Random access memory; Read-write memory; Timing;
Conference_Titel :
Electro International, 1991
Conference_Location :
New York, NY, USA
DOI :
10.1109/ELECTR.1991.718653
