• DocumentCode
    3530407
  • Title

    Burst Mode Memories Improve Cache Design

  • Author

    Amitai, Zwie ; Wyland, David C.

  • Author_Institution
    Quality Semiconductor, Inc.
  • fYear
    1991
  • fDate
    16-18 April 1991
  • Firstpage
    279
  • Lastpage
    282
  • Abstract
    Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.
  • Keywords
    Cache memory; Clocks; Counting circuits; Delay effects; Engineering management; Planing; Quality management; Random access memory; Read-write memory; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electro International, 1991
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ELECTR.1991.718653
  • Filename
    718653
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3530407