Fabrication of 0.1μm-gate InP HEMTs using i-line lithography

Author

Sawada, K. ; Makiyama, K. ; Takahashi, T. ; Nozaki, K. ; Igarashi, M. ; Kon, J. ; Hara, N.

Author_Institution

Fujitsu Labs. Ltd., Kanagawa, Japan

fYear

2003

fDate

12-16 May 2003

Firstpage

65

Lastpage

68

Abstract

We developed a new process (PATRASH: PAttern TRAnsfer SHrink) for fabricating T-shaped 0.1μm-gate InP HEMTs using i-line lithography. Higher throughput lithography processes were achieved by applying i-line lithography instead of electron beam (EB) lithography. The process we developed has three important technical aspects: shrinking the photoresist pattern, dry etching the multi-layer resists, and shrinking the PMMA resist. The controllability of gate lengths was good enough to realize circuit operation. Using our process, we fabricated a T-shaped 0.1μm-gate InP HEMT that showed a transconductance of 880 mS/mm and a cut-off frequency of 202 GHz. This performance equaled that of a device produced using EB lithography.

Keywords

III-V semiconductors; etching; high electron mobility transistors; indium compounds; lithography; semiconductor device measurement; 0.1 micron; 202 GHz; 880 mS/mm; InP; InP HEMTs; PMMA resist; dry etching; fabrication; i-line lithography; pattern transfer shrink; performance; photoresist; transconductance; Controllability; Dry etching; Electron beams; Fabrication; HEMTs; Indium phosphide; Lithography; MODFETs; Resists; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Indium Phosphide and Related Materials, 2003. International Conference on

Print_ISBN

0-7803-7704-4

Type

conf

DOI

10.1109/ICIPRM.2003.1205313

Filename

1205313