Fabrication of 0.1μm-gate InP HEMTs using i-line lithography

We developed a new process (PATRASH: PAttern TRAnsfer SHrink) for fabricating T-shaped 0.1μm-gate InP HEMTs using i-line lithography. Higher throughput lithography processes were achieved by applying i-line lithography instead of electron beam (EB) lithography. The process we developed has three important technical aspects: shrinking the photoresist pattern, dry etching the multi-layer resists, and shrinking the PMMA resist. The controllability of gate lengths was good enough to realize circuit operation. Using our process, we fabricated a T-shaped 0.1μm-gate InP HEMT that showed a transconductance of 880 mS/mm and a cut-off frequency of 202 GHz. This performance equaled that of a device produced using EB lithography.