Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems

Summary form only given. The goal of this tutorial is to explain the limits and opportunities of using silicon-photonic link technology for inter-chip and intra-chip communication in manycore systems. Silicon-photonic links have larger bandwidth density and lower energy than equivalent electrical links. In this tutorial, I will first provide an overview of the silicon-photonic device technology and link transceiver/tuning circuits. Using three silicon-photonic network case studies {on-chip tile-to-tile network, process-to-DRAM network and DRAM memory channel, the various silicon-photonic network design issues at the physical level, micro-architecture level and architecture level will be explained in detail. An iterative design process, where we move between these three levels to meet the power-performance specifications under the silicon-photonic technology constraints will also be presented. At the end of the tutorial, attendees will have a broad understanding of the capabilities of silicon-photonic technology, and they will be able to design and analyze silicon-photonic networks for Manycore systems.