Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing-based scheme.