• DocumentCode
    3531059
  • Title

    Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview

  • Author

    Garimella, Annajirao ; Surkanti, Punith ; Furth, Paul M.

  • Author_Institution
    New Mexico State Univ., Las Cruces, NM, USA
  • fYear
    2012
  • fDate
    7-11 Jan. 2012
  • Firstpage
    31
  • Lastpage
    32
  • Abstract
    Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.
  • Keywords
    poles and zeros; voltage regulators; circuit behavior; frequency compensation techniques; low-dropout voltage regulator; pole-zero analysis; small-signal model; transistor level design; voltage-current loop; Regulators; Tutorials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2012 25th International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4673-0438-2
  • Type

    conf

  • DOI
    10.1109/VLSID.2012.38
  • Filename
    6167719