Title :
A low-noise phase-locked loop with programmable gain VCO
Author_Institution :
Altera Corp., Bayan Lepas, Malaysia
Abstract :
In this paper, a phase-locked loop (PLL) with programmable gain VCO is proposed and analyzed. The proposed design adjusts the gain of the VCO based on the input frequency and the charge pump and loop filter settings in order to achieve lower phase noise. The proposed design is implemented using TSMC 45nm CMOS with a 0.9-V supply voltage. The pre-layout simulation shows that the random jitter of the system is improved when the VCO gain is reduced.
Keywords :
CMOS integrated circuits; charge pump circuits; phase locked loops; voltage-controlled oscillators; CMOS; charge pump; input frequency; loop filter; low-noise phase-locked loop; programmable gain VCO; size 45 nm; voltage 0.9 V; Bandwidth; Charge pumps; Clocks; Filters; Frequency; Jitter; Phase locked loops; Phase noise; Voltage control; Voltage-controlled oscillators; PLL; low noise; programmable;
Conference_Titel :
Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4244-7809-5
DOI :
10.1109/ASQED.2010.5548231
