Hardware Efficient Architecture for Generating Sine/Cosine Waves

Author

Aggarwal, Supriya ; Khare, Kavita

Author_Institution

Dept. of Electron. & Comm. Eng., NIT-Bhopal Maulana Azad Nat. Inst. of Technol., Bhopal, India

fYear

2012

fDate

7-11 Jan. 2012

Firstpage

57

Lastpage

61

Abstract

This paper presents a hardware efficient architecture for generating sine and cosine waves based on the CORDIC (Coordinate Rotation Digital Computer) algorithm. In its original form the CORDIC suffers from major drawbacks like scale-factor calculation, latency and optimal selection of micro-rotations. The proposed algorithm overcomes all these drawbacks. We use leading-one bit detection technique to identify the micro-rotations. The scale-free design of the proposed algorithm is based on Taylor series expansion of the sine and cosine waves. The 16-bit iterative architecture achieves approximately 4.5% and 6.7% lower slice-delay product as compared to the other existing designs. The algorithm design and its VLSI implementation are detailed.

Keywords

VLSI; delays; digital arithmetic; iterative methods; series (mathematics); waveform generators; CORDIC algorithm; Taylor series expansion; VLSI implementation; coordinate rotation digital computer algorithm; hardware efficient architecture; iterative architecture; leading-one bit detection technique; lower slice-delay product; microrotation optimal selection; scale-factor calculation; scale-free design; sine-cosine wave generation; word length 1 bit; word length 16 bit; Algorithm design and analysis; Approximation algorithms; Approximation methods; Computer architecture; Hardware; Signal processing algorithms; Taylor series; CORDIC Algorithm; Cosine; Leading-One Bit; Sine; Taylor Series;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design (VLSID), 2012 25th International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

978-1-4673-0438-2

Type

conf

DOI

10.1109/VLSID.2012.46

Filename

6167728