• DocumentCode
    3531284
  • Title

    Peak current reduction using an MTCMOS technique

  • Author

    Lu, Liang-Ying ; Wu, Tsung-Yi ; Chiou, Lih-Yih ; Shi, Jing-Wen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2010
  • fDate
    3-4 Aug. 2010
  • Firstpage
    255
  • Lastpage
    259
  • Abstract
    In a digital circuit system, IR drop effect can be alleviated by reducing the peak current of the system. Clock skew scheduling is a popular technique for peak current reduction. In this paper, we propose two algorithms that apply a Multiple Threshold CMOS (MTCMOS) technique rather than clock skew scheduling to do peak current reduction. MTCMOS techniques are feasible to reduce peak current because different threshold cells have different cell delays and current waveforms. Experimental results show that our technique can reduce the peak current up to 47.7%. Our proposed technique can reduce not only peak current but also leakage current. Moreover, a peak current reduction algorithm using a clock skew technique or an opposite-phase clock scheme can employ our proposed technique to further reduce the peak current of a circuit.
  • Keywords
    CMOS integrated circuits; clocks; digital circuits; scheduling; IR drop effect; clock skew scheduling; digital circuit system; multiple threshold CMOS technique; opposite-phase clock scheme; peak current reduction; CMOS logic circuits; CMOS technology; Clocks; Delay; Electronic design automation and methodology; Flip-flops; Leakage current; Logic circuits; Logic gates; Voltage; Clock skew technique; IR drop; MTCMOS; peak current;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
  • Conference_Location
    Penang
  • Print_ISBN
    978-1-4244-7809-5
  • Type

    conf

  • DOI
    10.1109/ASQED.2010.5548248
  • Filename
    5548248