Optimizing device size for soft error resilience in sub-micron logic circuits

As technology nodes are being scaled down, soft errors induced by particle strikes are becoming a troublesome reliability issue in logic circuits. Various sizing techniques commonly used to reduce soft error rate in the past are expensive in terms of area, performance, and energy consumption. These methods require changes to adapt to sub-micron technologies. This study introduces two novel sizing methods that selectively upsize transistor networks of a circuit. Our first proposed methodology formulates the soft error rate minimization as a mathematical optimization problem and searches for the best area distribution such that maximum reliability gain is obtained. This methodology assures that optimal solutions are achieved within given area budget provided to the designer. However, generating optimal solution requires very high CPU time. Therefore, we propose a heuristic based methodology which upsizes only selected transistor network in sensitive gates based on soft error sensitivity of each gate. With proper sensitive gate selection and area distribution algorithms proposed in this technique, we show through experimental results that our heuristic driven method gives satisfactory reliability improvement compared to our first method, while requiring relatively small computation time.