Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC

Author

Singh, Mohit ; Gupta, Shalabh

Author_Institution

Dept. of Electr. Eng., IIT Bombay, Mumbai, India

fYear

2012

fDate

7-11 Jan. 2012

Firstpage

96

Lastpage

100

Abstract

High-Speed Digital-to-Analog Converters (DACs) are inevitable due to the advent of multi level modulation formats to meet the increasing demand of high data rates in communication systems. In this paper, a 4-bit 20 GS/s DAC has been designed in 90 nm CMOS technology. CMOS based DACs provide a low cost single IC solution as compared to compound semiconductor counterparts by fully integrating digital and RF blocks. In this paper, an on-chip Linear Feedback Shift Register (LFSR) is used to generate the required high-speed broadband data and eye diagram of the DAC output is used for characterization. In order to drive the high capacitive loads along with routing, Electro Static Discharge (ESD) and pad capacitance (≈800 fF) at a speed of 20 GS/s (13.1 GHz bandwidth), a new buffer architecture has also been implemented.

Keywords

CMOS integrated circuits; digital-analogue conversion; electrostatic discharge; shift registers; CMOS DAC; ESD; RF blocks; bandwidth 13.1 GHz; buffer design; communication systems; compound semiconductor counterparts; electrostatic discharge; eye-diagram based characterization; high capacitive loads; high-speed broadband data; high-speed digital-to-analog converters; linear feedback shift register; low cost single IC solution; multilevel modulation formats; pad capacitance; size 90 nm; word length 4 bit; Bandwidth; Broadband communication; CMOS integrated circuits; CMOS technology; Capacitance; Resistance; Transistors; Characterizing High-Speed DACs; Eye-Diagram; High-speed buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design (VLSID), 2012 25th International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

978-1-4673-0438-2

Type

conf

DOI

10.1109/VLSID.2012.53

Filename

6167735