A case study of Short Term Cell-Flipping technique for mitigating NBTI degradation on cache

Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage shifts in the load transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. Because an SRAM cell consists of two inverters, one of the load transistors is always stressed. In order to mitigate NBTI degradation, we proposed Short Term Cell-Flipping technique (STCF) for SRAM cell. This technique makes the stress probability on load transistors in an SRAM cell close to 50%. In this paper, we apply STCF technique to cache memories, and discuss its potential to mitigate NBTI degradation.