DocumentCode :
3531542
Title :
Set-Cover Heuristics for Two-Level Logic Minimization
Author :
Kagliwal, Ankit ; Balachandran, Shankar
Author_Institution :
Comput. Sci. & Eng. Dept., Indian Inst. of Technol. Madras, Chennai, India
fYear :
2012
fDate :
7-11 Jan. 2012
Firstpage :
197
Lastpage :
202
Abstract :
Given a Boolean function, the Unate-Covering Problem (UCP) is NP-hard. This problem can be modeled as a set cover problem where minterms are the elements and implicants form the sets. Traditional solutions in logic synthesis use set cover algorithms that are oblivious to the special semantic of the elements and sets. We propose three new heuristics for the set-cover problem which are aware of the relationship between implicants and minterms. We show that the proposed heuristics are effective for breaking ties when a cyclic core is obtained. We evaluate the heuristics on a set of hard instances from BHOSLIB benchmark suite. We also replace ESPRESSO´s set cover algorithm using these heuristics and compare the logic synthesis results. We further map the minimized Boolean equations using ABC´s technology mapping tool using 2-input NAND gates and 4-input Lookup Tables (LUTs).
Keywords :
Boolean functions; computational complexity; logic gates; 2-input NAND gates; 4-input LUT; 4-input lookup tables; ABC technology; BHOSLIB benchmark suite; Boolean function; ESPRESSO set cover algorithm; NP-hard; UCP; logic synthesis; set-cover heuristics; set-cover problem; two-level logic minimization; unate-covering problem; Benchmark testing; Boolean functions; Field programmable gate arrays; Heuristic algorithms; Logic gates; Minimization; Table lookup; ESPRESSO-II; heuristic; set-cover; two-level logic minimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
978-1-4673-0438-2
Type :
conf
DOI :
10.1109/VLSID.2012.70
Filename :
6167752
Link To Document :
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