DocumentCode
3531654
Title
A Memory Built-In Self-Test Architecture for Memories Different in Size
Author
Rao, Quan-Lin ; He, Chun ; Jia, Yu-Ming
Author_Institution
Res. Inst. of Electron. Sci. & Technol., Univ. of Electron. & Since Technol. of China, Chengdu
fYear
2009
fDate
28-29 April 2009
Firstpage
1
Lastpage
4
Abstract
To reduce the area and developing time of the Memory Built-in Self-Test (MBIST) circuit has been challenged in the market. An architecture that could test memories different in size by only one MBIST circuit is presented in this paper. It is achieved by adding a data processing module and an address processing module into the mature and ready-made MBIST architecture. Base on this architecture, a MBIST circuit for the memories embedded in a SoC chip is successfully designed.
Keywords
built-in self test; memory architecture; memory built-in self-test architecture; Built-in self-test; Circuit testing; Consumer electronics; Data processing; Electronic design automation and methodology; Engines; Helium; Memory architecture; Read-write memory; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-2587-7
Type
conf
DOI
10.1109/CAS-ICTD.2009.4960752
Filename
4960752
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