A Mixed-Signal BIST Scheme for ADCs in SoC and its FPGA Implementation

Author

Yuan, Chao ; Zhao, Yuanfu ; Du, Jun ; Bao, Fang

Author_Institution

Dept. of designing, Beijing Microelectron. Technol. Inst., Beijing

fYear

2009

fDate

28-29 April 2009

Firstpage

1

Lastpage

4

Abstract

A novel Mixed-Signal BIST scheme that is capable of calculating dynamic and static parameters of ADCs is proposed. By elaborately integrating test capability of both dynamic and static test uniformly in one BIST circuit, as well as reusing and organizing the elemental operative units and memories for analog stimulus generation and response analysis, hardware overhead is restricted to the minimum with very little impact on test quality. The proposed scheme is implemented and verified in FPGA thereby validates the viability and flexibility of the design.

Keywords

analogue-digital conversion; built-in self test; field programmable gate arrays; logic testing; system-on-chip; ADC; FPGA; SoC; analog stimulus generation; analogue-digital conversion; built-in self test; dynamic test; field programmable gate arrays; mixed-signal BIST scheme; static test; system-on-chip; Automatic testing; Built-in self-test; Circuit testing; Field programmable gate arrays; Filtering; Frequency; Hardware; Random access memory; Signal generators; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-2587-7

Type

conf

DOI

10.1109/CAS-ICTD.2009.4960756

Filename

4960756