DocumentCode :
3531752
Title :
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs
Author :
Vudadha, Chetan ; Makkena, Goutham ; Nayudu, M. Venkata Swamy ; Phaneendra, P. Sai ; Ahmed, Syed Ershad ; Veeramachaneni, Sreehari ; Muthukrishnan, N. Moorthy ; Srinivas, M.B.
Author_Institution :
Dept. of Electr. Eng., Birla Inst. of Technol. & Sci.-Pilani, Hyderabad, India
fYear :
2012
fDate :
7-11 Jan. 2012
Firstpage :
280
Lastpage :
285
Abstract :
This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This ´self-reconfigurable´ property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.
Keywords :
analogue-digital conversion; binary codes; decoding; adaptive resolution analog-to-digital converters; adaptive resolution flash ADC; binary code; digital decoders; flash analog-to-digital converters; low operand length thermometer code; low-power self reconfigurable multiplexer based decoder; self-reconfigurable property; Binary codes; Decoding; Delay; Logic gates; Power demand; Read only memory; Switches; Flash converter; Low power; Multi-precision; Reconfigurable; Thermometer-to-binary;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
978-1-4673-0438-2
Type :
conf
DOI :
10.1109/VLSID.2012.84
Filename :
6167765
Link To Document :
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