DocumentCode
3531759
Title
A Novel BIST Approach for Testing DLLs of SoC
Author
Wang, Min ; Wen, Zhiping ; Chen, Lei ; Zhang, Yanlong ; Zhang, Zhiquan
Author_Institution
Beijing Microelectron. Tech. Instn. (BMTI), Beijing
fYear
2009
fDate
28-29 April 2009
Firstpage
1
Lastpage
4
Abstract
A novel Built-In-Self-Test (BIST) approach is present in this paper to test the clock manager DLL of system-on-chip (SoC). The whole approach is divided into two steps. Firstly, test a single DLL which will be used as the benchmark in step two by introducing a test clock which is the jitter embodiment of the reference clock. The proposed method with a view to test the reference clock jitter tolerance. In the second step, the purpose is testing all the DLLs of SoC by traditional BIST approach based on comparison. And use the output response analyzer (ORA) to judge the comparison result. The proposed approach is widely suitable for test DLL of SoC rapidly and simply without complex test equipments.
Keywords
built-in self test; clocks; delay lock loops; jitter; system-on-chip; BIST; DLL; SoC; clock manager; delay lock loop; jitter tolerance; output response analyzer; Benchmark testing; Built-in self-test; Circuit testing; Clocks; Delay; Jitter; Phase locked loops; System testing; System-on-a-chip; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-2587-7
Type
conf
DOI
10.1109/CAS-ICTD.2009.4960759
Filename
4960759
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