Title :
A Novel BIST Approach for Testing Input/Output Buffers in SOCs
Author :
Chen, Lei ; Wen, Zhiping ; Zhang, Zhiquan ; Min, Wang
Author_Institution :
Beijing Microelectron. Tech. Instn., Beijing
Abstract :
A novel Built-in Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series SOCs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs. Only total of 10 configurations are required to completely test the I/O buffers of Virtex devices.
Keywords :
built-in self test; field programmable gate arrays; logic testing; system-on-chip; BIST approach; FPGA; SOC; Xilinx Virtex series; built-in self-test; hard macro; input buffer testing; multiple stuck-at gate-level fault; output buffer testing; routing resource; Automatic testing; Built-in self-test; Counting circuits; Field programmable gate arrays; Flip-flops; Hardware design languages; Logic testing; Microelectronics; Multiplexing; Routing;
Conference_Titel :
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-2587-7
DOI :
10.1109/CAS-ICTD.2009.4960760
