DocumentCode :
3531960
Title :
Dispatching In An Integrated Circuit Wafer Fabrication Line
Author :
John, P.K.
Author_Institution :
AT&T Bell Laboratories
fYear :
1989
fDate :
4-6 Dec 1989
Firstpage :
918
Lastpage :
921
Keywords :
Delay effects; Discrete event simulation; Dispatching; Dynamic scheduling; Electric breakdown; Fabrication; Job shop scheduling; Pulp manufacturing; Scheduling algorithm; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation Conference Proceedings, 1989. Winter
Print_ISBN :
0-911801-58-8
Type :
conf
DOI :
10.1109/WSC.1989.718773
Filename :
718773
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3531960
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