Effect of high tensile Inter Layer Dielectric on hook shaped Idsat characteristics of 0.13um CMOS technology

In this paper, we demonstrate that by introducing a high tensile Inter Layer Dielectric (ILD) in the fabrication process, the hook shaped saturation drain current (Idsat) behavior of NMOS can be reduced and totally eliminated in PMOS for 0.13um technology node. The hook shaped Idsat behavior is caused by the combination of mechanical stress due to Shallow Trench Isolation (STI) in channel width direction and relatively more significant delta width effect in narrow devices. This paper investigates how the tensile ILD layer on top of the transistor impacts both the NMOS and the PMOS devices in terms of STI stress in channel length direction (x-stress) and channel width direction (y-stress).