• DocumentCode
    3532073
  • Title

    A Novel SMT-Based Technique for LFSR Reseeding

  • Author

    Prabhu, Sarvesh ; Hsiao, Michael S. ; Lingappan, Loganathan ; Gangaram, Vijay

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
  • fYear
    2012
  • fDate
    7-11 Jan. 2012
  • Firstpage
    394
  • Lastpage
    399
  • Abstract
    In order for logic built-in-self-test (LBIST) to achieve coverages comparable with deterministic tests, multiple (and frequently many) seeds are often needed. Unlike previous methods that attempt to chain/compact the number of seeds, we present a novel Satisfiability Modulo Theory (SMT) based technique that can reduce the number of seeds significantly while simultaneously achieving high coverage for LBIST. In this technique we integrate the process of deterministic test generation and seed generation in one SMT process to eliminate the problems of chaining the separately generated deterministic patterns. Experimental results show the promise of the approach.
  • Keywords
    built-in self test; logic testing; LBIST; LFSR reseeding; SMT process; SMT-based technique; logic built-in-self-test; satisfiability modulo theory based technique; seed generation; test generation; Automatic test pattern generation; Circuit faults; Logic gates; Polynomials; System-on-a-chip; Vectors; LBIST; LFSR-reseeding; SMT;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2012 25th International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4673-0438-2
  • Type

    conf

  • DOI
    10.1109/VLSID.2012.103
  • Filename
    6167784