Title :
Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM
Author :
Srinivasaiah, H.C.
Author_Institution :
Dept. of Telecommun. Eng., Dayananda Sagar Coll. of Eng. (DSCE), Bangalore, India
Abstract :
Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.
Keywords :
MOSFET; SRAM chips; leakage currents; masks; NMOS driver transistor; SRAM cell; backscattering; current 22 nA; damped oscillatory curve; device leakage current; halo implant mask layer thickness; halo implant shadowing; implant window width; mask layer edges; size 120 nm; size 500 nm; size 65 nm; voltage 1.2 V; Implants; Leakage current; Logic gates; MOS devices; Random access memory; Shadow mapping; Transistors; 65nm process technology; 6T-SRAM; Embedded SRAM; Halo implantation; Low power SRAM; Process technology; Shadow effect;
Conference_Titel :
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
978-1-4673-0438-2
DOI :
10.1109/VLSID.2012.106